1. Field of the Invention
The present invention relates to a communication data transfer device, and more particularly to a data transfer device acquiring data stored in memory and executing an alignment process for packet communications.
2. Description of Related Art
In association with progress and wide use of network technology as represented by the Internet, many computers are connected to networks for data communication with other computers. Typically, a computer is connected to a LAN (Local Area Network), as represented by Ethernet, for data communications with other computers within the LAN, and connected to external networks via the LAN.
Data is transferred via a network controller within the computer. The network controller executes the necessary processing for data acquired from the main memory, and outputs the created packet data to the LAN. Furthermore, the necessary processing for the packet data acquired from the LAN is executed, and that data is stored in the main memory. FIG. 4 is a block diagram illustrating data processing for data transfer using a related technique.
FIG. 4 shows the aligner 310 which consists a part of the network controller, and the main memory 350 which stores data. The aligner 310 and main memory 350 send and receive data via the data bus 360. The aligner 310 incorporates alignment logic 311 to align acquired data in a sequence for packet communications on the network. Furthermore, the aligner 310 also incorporates the FIFO 312 temporarily store data from the alignment logic 311 and output the stored data in the order of storage, and the sequencer 313 controlling reading of data from the main memory 350 and output of data from the FIFO 312.
In FIG. 4, aligned data is stored in the FIFO 312. Each square in the FIFO 312 represents one byte of data. Furthermore, the hatched squares represent communication data valid for transfer, and the white squares represent communication data invalid for transfer. The alignment logic 311 aligns valid data into a contiguous sequence of data as shown in FIG. 4 from data comprising both invalid and valid data.
Data transfer processing in the system shown in FIG. 4, in particular, output processing of data stored in the main memory 350, is described below. Firstly, the sequencer 313 issues a request to read data from the main memory 350 (MReq) ([1]). In response to the request, the data RDATA is read from the main memory 350, and provided to the alignment logic 311 of the aligner 310 ([2]). The alignment logic 311 aligns the acquired data, and outputs ALRDATA to FIFO 312 ([3]).
After transfer of data from the main memory 350 to the aligner 310 is completed, MAck indicating the completion is sent to the sequencer 313 ([4]). In response to MAck, the sequencer 313 outputs the Ctl signal controlling the FIFO 312 so that the data in the FIFO 312 is output in the next data processing block ([5]). This processing is repeated until no data remains to transfer. Additionally, a storage buffer with a plurality of data registers which processes a store request from the CPU to the memory is disclosed in Japanese Patent Application Laid-open No. 61-118853.
In the technique described with reference to FIG. 4, data input from the main memory main memory 350 to the alignment logic 311 requires waiting for completion of output of the prescribed number of bytes from the FIFO 312. For example, when 64 bytes of data are read from the main memory 350, it is needed that the full FIFO 312 outputs 64 bytes of data to prepare free space sufficient for storage of 64 bytes of data, and data is then transferred from the main memory 350.
It has now been discovered that, however, since other circuit configurations also use data bus 360, it may not be possible to start data transfer from the main memory 350 at the timing when free space becomes available in the FIFO 312. If data cannot be read from the main memory 350 at the desired timing, dead time is introduced to delay data transfer.
In particular, the speed of data transfer in networks is increasing in association with recent progress in semiconductor technology and data processing technology. For example, Ethernet data transfer speed has increased from 10 Mbps, to 100 Mbps, and subsequently to 1 Gbps. Thus, latency from the main memory 350 to the aligner 310 can form a bottleneck, and cause an inability to accommodate external data transfer speeds.
Additionally, it is necessary to input data read from the main memory 350 to the FIFO in the sequence in which it was read. Thus, read commands must be issued and completed individually and independently, and the efficiency of the bus use cannot be improved by interleaving the commands.